tmp/tmpb7w5ksbp/{from.md → to.md}
RENAMED
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@@ -27,11 +27,11 @@ release sequence headed by *A*.
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``` cpp
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extern "C" void atomic_thread_fence(memory_order order) noexcept;
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```
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-
*Effects:*
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- has no effects, if `order == memory_order_relaxed`;
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- is an acquire fence, if
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`order == memory_order_acquire || order == memory_order_consume`;
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- is a release fence, if `order == memory_order_release`;
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@@ -46,32 +46,30 @@ extern "C" void atomic_signal_fence(memory_order order) noexcept;
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*Effects:* Equivalent to `atomic_thread_fence(order)`, except that the
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resulting ordering constraints are established only between a thread and
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a signal handler executed in the same thread.
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-
*Note
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actions performed by the thread become visible to the signal
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-
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*Note:* compiler optimizations and reorderings of loads and stores are
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inhibited in the same way as with `atomic_thread_fence`, but the
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hardware fence instructions that `atomic_thread_fence` would have
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inserted are not emitted.
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<!-- Link reference definitions -->
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[atomics]: #atomics
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[atomics.fences]: #atomics.fences
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[atomics.flag]: #atomics.flag
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[atomics.general]: #atomics.general
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[atomics.lockfree]: #atomics.lockfree
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[atomics.order]: #atomics.order
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[atomics.syn]: #atomics.syn
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[atomics.types.generic]: #atomics.types.generic
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[atomics.types.operations]: #atomics.types.operations
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-
[atomics.types.
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[atomics.types.operations.general]: #atomics.types.operations.general
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-
[atomics.types.operations.pointer]: #atomics.types.operations.pointer
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[atomics.types.operations.req]: #atomics.types.operations.req
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[atomics.types.operations.templ]: #atomics.types.operations.templ
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[basic.types]: basic.md#basic.types
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[intro.multithread]: intro.md#intro.multithread
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[
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[tab:atomics.typedefs]: #tab:atomics.typedefs
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``` cpp
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extern "C" void atomic_thread_fence(memory_order order) noexcept;
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```
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+
*Effects:* Depending on the value of `order`, this operation:
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- has no effects, if `order == memory_order_relaxed`;
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- is an acquire fence, if
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`order == memory_order_acquire || order == memory_order_consume`;
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- is a release fence, if `order == memory_order_release`;
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*Effects:* Equivalent to `atomic_thread_fence(order)`, except that the
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resulting ordering constraints are established only between a thread and
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a signal handler executed in the same thread.
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+
[*Note 1*: `atomic_signal_fence` can be used to specify the order in
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which actions performed by the thread become visible to the signal
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handler. Compiler optimizations and reorderings of loads and stores are
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inhibited in the same way as with `atomic_thread_fence`, but the
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hardware fence instructions that `atomic_thread_fence` would have
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inserted are not emitted. — *end note*]
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<!-- Link reference definitions -->
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[atomics]: #atomics
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[atomics.alias]: #atomics.alias
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[atomics.fences]: #atomics.fences
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[atomics.flag]: #atomics.flag
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[atomics.general]: #atomics.general
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[atomics.lockfree]: #atomics.lockfree
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[atomics.nonmembers]: #atomics.nonmembers
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[atomics.order]: #atomics.order
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[atomics.syn]: #atomics.syn
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[atomics.types.generic]: #atomics.types.generic
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[atomics.types.int]: #atomics.types.int
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[atomics.types.memop]: #atomics.types.memop
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[atomics.types.operations]: #atomics.types.operations
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[atomics.types.pointer]: #atomics.types.pointer
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[basic.types]: basic.md#basic.types
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[intro.multithread]: intro.md#intro.multithread
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[intro.progress]: intro.md#intro.progress
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